Ripple Carry Adder

Ripple Carry Adder

 

AIM: To develop HDL code for Ripple Carry Adder

Tools/Software Required:

1.                       Personal Computer.

2.                       Vivado 2019.2 Software

3.                       Verilog/VHDL

Procedure:

1.                     Click on Vivado2017.2 icon.A window is opened.

2.                     Click on File→New Project→Press Next→Give the Project name and Project Location→Press Next→Choose Project Type as RTL Project→Press Next→

3.                     Create File→File Type: VHDL\Verilog File Name→ Filename→Press Next→ Press Next→ Press Next→Finish.

4.                     Write the module definition by giving input ports and output ports  →Press Ok.

5.                     Two workspaces are opened with names Project Manager and Flow Navigator

6.                     In Project Manager  →Click on Sources →Design Sources→File→A window is opened with File name. Write the Program in the File →Click on Save.

7.                     In Flow Navigator→Click on Simulation  →Run Simulation→Run Behavioural Simulation→A window is opened with name “untitled1”→Force Constants→Run for 100 µs. Observe the simulation results for various combinations by clicking on Zoom Out.

Verilog Code

module rca_g1(

    output [1:0] s,

    output cout,

    input [1:0] a,

    input [1:0] b,

    input cin

    );

    wire c1;

    fulladder x1(s[0],c1,a[0],b[0],cin);

    fulladder x2(s[1],cout,a[1],b[1],c1);

endmodule

module fulladder(s,c,a,b,c1);

output s,c;

input a,b,c1;

wire x,y,z;

xor x1(s,a,b,c1);

and a1(x,a,b);

and a2(y,b,c1);

and a3(z,c1,a);

or o(c,x,y,z);

 endmodule

RTL Schematics for Ripple Carry Adder

         Internal RTL of Full Adder 

Simulation Waveform for Ripple Carry Adder

Result:

The Ripple Carry Adder is simulated using Vivado2019.1 software on an I3 Processor with 64-bit Operating System