Verilog Code for 8:1 Multiplexer in different styles

  AIM:  To develop HDL Program for 8:1 Multiplexer in different styles

 

Tools/Software Required:

1.                                                         Personal Computer.

2.                                                         Vivado 2019.2 Software

3.                                                         Verilog

Procedure:

1.                  Click on Vivado2017.2 icon.A window is opened.

2.                  Click on File→New Project→Press Next→Give the Project name and Project Location→Press Next→Choose Project Type as RTL Project→Press Next→

3.                  Create File→File Type: VHDL\VERILOG File Name→ Filename→Press Next→ Press Next→ Press Next→Finish.

4.                  Write the module definition by giving input ports and output ports  →Press Ok.

5.                  Two workspaces are opened with names Project Manager and Flow Navigator

6.                  In Project Manager  →Click on Sources →Design Sources→File→A window is opened with File name. Write the Program in the File →Click on Save.

7.                  In Flow Navigator→Click on Simulation  →Run Simulation→Run Behavioural Simulation→A window is opened with name “untitled1”→Force Constants→Run for 100 µs. Observe the simulation results for various combinations by clicking on Zoom Out.

Verilog Code for 8:1 Multiplexer

 

Data flow Modelling

module mux81(

    input a,b,c,d,e,f,g,h,

    input s2,s1,s0,

    output y

    );

    assign y= s2?(s1?(s0?h:g):(s0?f:e)):(s1?(s0?d:c):(s0?b:a));

endmodule

        Behavioural Modelling

        Version 1:

      

module mux81b(

    

    input [7:0] i,

    input [2:0] s,

    output reg y

    );

always @ (*)

begin

case (s)

3'b000 : y <= i[0];

3'b01 : y <= i[1];

3'b10 : y <= i[2];

3'b11 : y <= i[3];

3'b100 : y <= i[4];

3'b101 : y <= i[5];

3'b110 : y <= i[6];

3'b111 : y <= i[7];

endcase

end

endmodule  

    

      Gate Level  Modelling

     module mux81bc(

    input a,b,c,d,e,f,g,h,input s2,s1,s0,

    output y

    );

    wire [2:0]sb;

    wire [8:1]x;

   not (sb[1],s1); 

    not (sb[0],s0);

    not (sb[2],s2);

    and (x[1],sb[2],sb[1],sb[0],a);

     and (x[2],sb[2],sb[1],s0,b);

      and (x[3],sb[2],s1,sb[0],c);

      and (x[4],sb[2],s1,s0,d);

      and (x[5],s2,sb[1],sb[0],e);

      and (x[6],s2,sb[1],s0,f);

      and (x[7],s2,s1,sb[0],g);

      and (x[8],s2,s1,s0,h);

      or (y, x[1],x[2],x[3],x[4],x[5],x[6],x[7],x[8]);

endmodule