Verilog code for 2:1 Multiplexer in different styles

         AIM:  To develop HDL Program for 2:1 Multiplexer in different styles

 

Tools/Software Required:

1.                                                         Personal Computer.

2.                                                         Vivado 2019.2 Software

3.                                                         Verilog/VHDL

Procedure:

1.                  Click on Vivado2017.2 icon.A window is opened.

2.                  Click on File→New Project→Press Next→Give the Project name and Project Location→Press Next→Choose Project Type as RTL Project→Press Next→

3.                  Create File→File Type: VHDL\VERILOG File Name→ Filename→Press Next→ Press Next→ Press Next→Finish.

4.                  Write the module definition by giving input ports and output ports  →Press Ok.

5.                  Two workspaces are opened with names Project Manager and Flow Navigator

6.                  In Project Manager  →Click on Sources →Design Sources→File→A window is opened with File name. Write the Program in the File →Click on Save.

7.                  In Flow Navigator→Click on Simulation  →Run Simulation→Run Behavioural Simulation→A window is opened with name “untitled1”→Force Constants→Run for 100 µs. Observe the simulation results for various combinations by clicking on Zoom Out.

Verilog Code for 2:1 Multiplexer

 

Data flow Modelling

module mux21(
    input i0,i1,s,
    output y
    );
    assign y=s?i0:i1;
endmodule

        Behavioural Modelling

        Version 1:

        module mux21b(

            input a,b,s,

            output  reg y

            );

            always @(*)

            begin

            if (s)

            y=a;

            else y=b;

            end

            endmodule

         Version 2:

          module mux21d(

                    input i0,i1,s,

                    output  reg y );

              always @( *)

                begin

                      case (s)

                      1'b0:y=i1;

                      1'b1:y=i0;

                    

                      endcase

                      end

                      endmodule

      Gate Level  Modelling

                        module mux21c(

                        input a,b,s,

                        output y

                            );

                            wire x1,x2,sb;

                              not (sb,s);

                                and (x1,sb,b);

                                and (x2,s,a);

                                or (y,x1,x2);

    

                            endmodule
Test Bench

`timescale 1ns/1ps

module mux21_testbench;

    // Declare testbench variables

    reg i0, i1, s;

    wire y_df, y_bv1, y_bv2, y_gl;

    // Instantiate modules for different implementations

    mux21 uut_df (

        .i0(i0),

        .i1(i1),

        .s(s),

        .y(y_df)

    );

    mux21b uut_bv1 (

        .a(i0),

        .b(i1),

        .s(s),

        .y(y_bv1)

    );

    mux21d uut_bv2 (

        .i0(i0),

        .i1(i1),

        .s(s),

        .y(y_bv2)

    );

    mux21c uut_gl (

        .a(i0),

        .b(i1),

        .s(s),

        .y(y_gl)

    );

    // Stimulus process

    initial begin

        // Display header for results

        $display("Time | i0 | i1 | s | DataFlow | BehavV1 | BehavV2 | GateLevel");

        $monitor("%4t |  %b  |  %b  | %b |    %b     |    %b    |    %b    |    %b",

                 $time, i0, i1, s, y_df, y_bv1, y_bv2, y_gl);

        // Apply test vectors

        i0 = 0; i1 = 0; s = 0; #10;

        i0 = 0; i1 = 1; s = 0; #10;

        i0 = 1; i1 = 0; s = 0; #10;

        i0 = 1; i1 = 1; s = 0; #10;

        i0 = 0; i1 = 0; s = 1; #10;

        i0 = 0; i1 = 1; s = 1; #10;

        i0 = 1; i1 = 0; s = 1; #10;

        i0 = 1; i1 = 1; s = 1; #10;

        // End simulation

        $finish;

    end

endmodule