Verilog Code for 16:1 Multiplexer in different styles

  AIM:  To develop HDL Program for 16:1 Multiplexer in different styles

 

Tools/Software Required:

1.                                                         Personal Computer.

2.                                                         Vivado 2019.2 Software

3.                                                         Verilog

Procedure:

1.                  Click on Vivado2017.2 icon.A window is opened.

2.                  Click on File→New Project→Press Next→Give the Project name and Project Location→Press Next→Choose Project Type as RTL Project→Press Next→

3.                  Create File→File Type: VHDL\VERILOG File Name→ Filename→Press Next→ Press Next→ Press Next→Finish.

4.                  Write the module definition by giving input ports and output ports  →Press Ok.

5.                  Two workspaces are opened with names Project Manager and Flow Navigator

6.                  In Project Manager  →Click on Sources →Design Sources→File→A window is opened with File name. Write the Program in the File →Click on Save.

7.                  In Flow Navigator→Click on Simulation  →Run Simulation→Run Behavioural Simulation→A window is opened with name “untitled1”→Force Constants→Run for 100 µs. Observe the simulation results for various combinations by clicking on Zoom Out.

Verilog Code for 16:1 Multiplexer

 

Data flow Modelling

module mux16(

    input [15:0] i,

    input [3:0] s,

    output y

    );

    assign y= (s==4'd15)? i[15]:(s==4'd0)?i[0]:(s==4'd1)?i[1]:(s==4'd2)?i[2]:(s==4'd3)?i[3]:(s==4'd4)?i[4]

    :(s==4'd5)?i[5]:(s==4'd6)?i[6]:(s==4'd7)?i[7]:(s==4'd8)?i[8]:

    (s==4'd9)?i[9]:(s==4'd10)?i[10]:(s==4'd11)?i[11]:(s==4'd12)?i[12]:

    (s==4'd13)?i[13]:(s==4'd14)?i[14]:0;

    

endmodule

        Behavioural Modelling

        Version 1:

      module mux16b(

    input [15:0] i,

    input [3:0] s,

    output reg y

    );

always @ (*)

begin

case (s)

4'b00 : y <= i[0];

4'b01 : y <= i[1];

4'b10 : y <= i[2];

4'b11 : y <= i[3];

4'b100 : y <= i[4];

4'b101 : y <= i[5];

4'b110 : y <= i[6];

4'b111 : y <= i[7];

4'd8 : y <= i[8];

4'd9:y <= i[9];

4'd10:y <= i[10];

4'd11:y <= i[11];

4'd12:y <= i[12];

4'd13:y <= i[13];

4'd14:y <= i[14];

4'd15:y <= i[15];

endcase

end

endmodule  

    

    

      Gate Level Modelling

     ///////////////////////////////////////////////

module mux16bc(

    input [15:0] x,

    input [3:0] s,

    output y

    );

    wire [15:0]d;

    wire [3:0]sb;

     not (sb[0],s[0]);

      not (sb[1],s[1]);

       not (sb[2],s[2]);

        not (sb[3],s[3]);

        and (d[0],sb[3],sb[2],sb[1],sb[0],x[0]);

        and (d[1],sb[3],sb[2],sb[1],s[0],x[1]);

        and (d[2],sb[3],sb[2],s[1],sb[0],x[2]);

        and (d[3],sb[3],sb[2],s[1],s[0],x[3]);

        and (d[4],sb[3],s[2],sb[1],sb[0],x[4]);

        and (d[5],sb[3],s[2],sb[1],s[0],x[5]);

        and (d[6],sb[3],s[2],s[1],sb[0],x[6]);

        and (d[7],sb[3],s[2],s[1],s[0],x[7]);

         and (d[8],s[3],sb[2],sb[1],sb[0],x[8]);

          and (d[9],s[3],sb[2],sb[1],s[0],x[9]);

           and (d[10],s[3],sb[2],s[1],sb[0],x[10]);

            and (d[11],s[3],sb[2],s[1],s[0],x[11]);

             and (d[12],s[3],s[2],sb[1],sb[0],x[12]);

              and (d[13],s[3],s[2],sb[1],s[0],x[13]);

               and (d[14],s[3],s[2],s[1],sb[0],x[14]);

                and (d[15],s[3],s[2],s[1],s[0],x[15]);

     

        or (y, d[0],d[1],d[2],d[3],d[4],d[5],d[6],d[7],d[8],d[9],d[10],d[11],d[12],d[13],d[14],d[15]);

endmodule