Logic gates in different Styles

 AIM:  To develop HDL Program for logic gates in different styles

 

Tools/Software Required:

1.                                                         Personal Computer.

2.                                                         Vivado 2019.2 Software

3.                                                         Verilog

Procedure:

1.                  Click on Vivado2017.2 icon.A window is opened.

2.                  Click on File→New Project→Press Next→Give the Project name and Project Location→Press Next→Choose Project Type as RTL Project→Press Next→

3.                  Create File→File Type: VHDL\VERILOG File Name→ Filename→Press Next→ Press Next→ Press Next→Finish.

4.                  Write the module definition by giving input ports and output ports  →Press Ok.

5.                  Two workspaces are opened with names Project Manager and Flow Navigator

6.                  In Project Manager  →Click on Sources →Design Sources→File→A window is opened with File name. Write the Program in the File →Click on Save.

7.                  In Flow Navigator→Click on Simulation  →Run Simulation→Run Behavioural Simulation→A window is opened with name “untitled1”→Force Constants→Run for 100 µs. Observe the simulation results for various combinations by clicking on Zoom Out.

Verilog Code for Logic gates

 Version1

module lg(

    input a,b,

    output [7:0] y

    );

    assign y[0]= a & b;

    assign y[1]=a | b;

    assign y[2]= a ^ b;

    assign y[3]=~(a & b);

    assign y[4]=~(a | b);

    assign y[5]= ~(a ^ b);

    assign y[6]= ~a;

    assign y[7]= ~b;

endmodule

  Version2

module lg1(

    input a,b,

    output [8:1] y

    );

    nand (y[1],a,b);

    nor (y[2],a,b);

    and (y[3],a,b);

    or (y[4],a,b);

    xor (y[5],a,b);

    xnor (y[6],a,b);

    not (y[7],a);

    not (y[8],b);

endmodule

 Version3

module lg3(

    input a,b,

    output [5:0]y

    );

    assign y[0]=a?b:0;//and gate

    assign y[1]=a?1:b;//Or gate

     assign y[2]=a?~b:1;//nand gate

      assign y[3]=a?0:~b;// nor gate

      assign y[4]=a?~b:b;//xor gate

      assign y[5]=a?b:~b;// xnor gate

      

endmodule