Encoder

8:3 Encoder

 

AIM: To develop HDL code for 8:3 Encoder.

Tools/Software Required:

1.                       Personal Computer.

2.                       Vivado 2019.2 Software

3.                       Verilog/VHDL

Procedure:

1.                     Click on Vivado2017.2 icon.A window is opened.

2.                     Click on File→New Project→Press Next→Give the Project name and Project Location→Press Next→Choose Project Type as RTL Project→Press Next→

3.                     Create File→File Type: VHDL\Verilog File Name→ Filename→Press Next→ Press Next→ Press Next→Finish.

4.                     Write the module definition by giving input ports and output ports  →Press Ok.

5.                     Two workspaces are opened with names Project Manager and Flow Navigator

6.                     In Project Manager  →Click on Sources →Design Sources→File→A window is opened with File name. Write the Program in the File →Click on Save.

7.                     In Flow Navigator→Click on Simulation  →Run Simulation→Run Behavioural Simulation→A window is opened with name “untitled1”→Force Constants→Run for 100 µs. Observe the simulation results for various combinations by clicking on Zoom Out.

VHDL Code  for 8:3 Encoder

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity encoder is

    Port ( en : in STD_LOGIC;

           a_in : in STD_LOGIC_VECTOR (7 downto 0);

           y_op : out STD_LOGIC_VECTOR (2 downto 0));

end encoder;

architecture Behavioral of encoder is

begin

process(en,a_in)

begin

if(en='1') then

y_op <= "ZZZ";

else

case(a_in) is 

when "00000001" => y_op <= "000";

when "00000010" => y_op <= "001";

when "00000100" => y_op <= "010";

when "00001000" => y_op <= "011";

when "00010000" => y_op <= "100";

when "00100000" => y_op <= "101";

when "01000000" => y_op <= "110";

when "10000000" => y_op <= "111";

when others => null;

end case;

end if;

end process; 

end Behavioral;

RTL Schematics for 8:3 Encoder



Simulation Waveform for 8:3 Encoder





Verilog Program for 8:3 Encoder:

module Encod(d0,d1,d2,d3,d4,d5,d6,d7,x,y,z);

input d0,d1,d2,d3,d4,d5,d6,d7;

output x,y,z;

or(x,d4,d5,d6,d7);

or(y,d2,d3,d6,d7);

or(z,d1,d3,d5,d7);

endmodule

 

RTL Schematics for 8:3 Encoder:



Simulation Waveform for 8:3 Encoder:



Result:

The 8:3 encoder is simulated using Vivado2019.1 software on an I3 Processor with 64-bit Operating System 

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