Encoder in different Styles

 8:3 Encoder

 

AIM: To develop HDL code for 8:3 Encoder.

Tools/Software Required:

1.                       Personal Computer.

2.                       Vivado 2019.2 Software

3.                       Verilog/VHDL

Procedure:

1.                     Click on Vivado2017.2 icon.A window is opened.

2.                     Click on File→New Project→Press Next→Give the Project name and Project Location→Press Next→Choose Project Type as RTL Project→Press Next→

3.                     Create File→File Type: VHDL\Verilog File Name→ Filename→Press Next→ Press Next→ Press Next→Finish.

4.                     Write the module definition by giving input ports and output ports  →Press Ok.

5.                     Two workspaces are opened with names Project Manager and Flow Navigator

6.                     In Project Manager  →Click on Sources →Design Sources→File→A window is opened with File name. Write the Program in the File →Click on Save.

7.                     In Flow Navigator→Click on Simulation  →Run Simulation→Run Behavioural Simulation→A window is opened with name “untitled1”→Force Constants→Run for 100 µs. Observe the simulation results for various combinations by clicking on Zoom Out.

Version1

module Encod(d0,d1,d2,d3,d4,d5,d6,d7,x,y,z);

input d0,d1,d2,d3,d4,d5,d6,d7;

output x,y,z;

or(x,d4,d5,d6,d7);

or(y,d2,d3,d6,d7);

or(z,d1,d3,d5,d7);

endmodule

 Version2

module encoder3(

input [7:0]  in,

input en,

output reg[2:0] out );

 always @( *)

begin

      if (en) 

        begin

          out=8'd0;

          case (in)

              8'b1: out=3'b0;

              8'b10: out=3'b1;

              8'b100: out=3'b010;

              8'b1000: out=3'b011;

              8'b10000: out=3'b100;

              8'b100000: out=3'b101;

              8'b1000000: out=3'b110;

              8'b10000000: out=3'b111;

              default: out=8'd0;

          endcase

      end

else 

out=8'd0;

end

endmodule

Version3

module Encod2(d0,d1,d2,d3,d4,d5,d6,d7,x,y,z);

input d0,d1,d2,d3,d4,d5,d6,d7;

output x,y,z;

assign x=d4|d5|d6|d7;

assign y=d2|d3|d6|d7;

assign z=d1|d3|d5|d7;

endmodule